PLL Loop Filter Designer
Designs the passive RC loop filter for a type-2, 3rd-order charge-pump PLL. Given the VCO gain, charge pump current, divider ratio, desired loop bandwidth, and phase margin, it calculates R, C₁, and C₂ values. The optional C₂ adds a 3rd pole to attenuate reference spurs.
Equations & Parameters ▸
\(G(s) = \dfrac{I_{cp}\cdot K_{vco}}{2\pi N\cdot s} \cdot F(s) \qquad F(s)=\dfrac{1+sRC_1}{sC_1(1+sRC_2)}\)
\(T_2 = RC_1 = \dfrac{\sin\phi_m}{\omega_c(1-\sin\phi_m)} \quad T_1 = \dfrac{1}{\omega_c^2 T_2} \quad C_1 = \dfrac{I_{cp}K_{vco}}{2\pi N}\cdot\dfrac{\sqrt{1+(\omega_c T_2)^2}}{\omega_c^2 T_1}\)
\(T_2 = RC_1 = \dfrac{\sin\phi_m}{\omega_c(1-\sin\phi_m)} \quad T_1 = \dfrac{1}{\omega_c^2 T_2} \quad C_1 = \dfrac{I_{cp}K_{vco}}{2\pi N}\cdot\dfrac{\sqrt{1+(\omega_c T_2)^2}}{\omega_c^2 T_1}\)
| Icp | Charge pump current (A) — from PLL IC datasheet |
| Kvco | VCO sensitivity (MHz/V or GHz/V). The tool converts to rad/s/V internally. |
| N | Total divide ratio (integer or fractional) |
| φm | Phase margin. 45–60° is typical; larger = more stable but slower locking |
| ωc | Loop bandwidth (rad/s). 1/10 to 1/20 of reference frequency to minimize spurs. |
PLL Parameters
A
°
Results
Diagram